1. Field of the Invention
The present invention relates to a semiconductor memory device control method suitable for application in DRAM (Dynamic Random Access Memory) which requires a refresh operation, and a semiconductor memory device.
2. Description of the Related Art
Recent semiconductor memory devices such as DRAM are used as well in mobile terminal devices such as portable telephones, PDA (Personal Digital Assistance), and the like, so that a reduction in current consumption is increasingly required for the semiconductor memory devices.
As a means for realizing a reduction in current consumption, Japanese Patent Application Laid-open No. 8-203268, for example, discloses a technique which places bit lines in a floating state in a non-access period for memory cells which hold data to eliminate leak currents flowing through bit lines and sense amplifiers connected thereto, thereby reducing the current consumption. The non-access period refers to a period which excludes a data read, a data write, and a refresh operation period. The refresh operation in turn refers to the operation for holding data written in memory cells by reading, amplifying, and rewriting the data every predetermined time.
DRAM is so structured as to hold data therein by accumulating charges on capacitors included in memory cells. With this structure, DRAM requires the refresh operation for reading data from the memory cells and rewriting the data into the memory cells within maximal data hold time tREFmax for which the memory cells can hold the data written therein. Average current consumption of DRAM depends on tREFmax, so that as DRAM has longer tREFmax, DRAM can reduce the number of times the refresh operation should be performed to result in a reduction in average current consumption.
However, even if the performance of memory cells and the like is improved to extend maximal data hold time tREFmax, the average current consumption cannot be reduced more after maximal data hold time tREFmax has reached a certain length. This is attributed to a current consumed by peripheral circuits, and the existence of a DC current component such as a leak current which flows into defective sites that were unintentionally fabricated in DRAM during the manufacturing.
As a result of increasingly higher integration of DRAM, a memory array unit of DRAM including a memory cell array comprising memory cells arranged in matrix, word drivers for driving word lines, sense amplifiers for reading data held in the memory cell array, and the like is processed for further miniaturization, as compared with peripheral circuits of DRAM. Thus, the highly miniaturized memory array unit suffers from a larger number of defects, such as short-circuit between adjacent lines, and the like, as compared with the peripheral circuits, resulting in the consumption of a current from an external power supply due to leak currents which may have been generated at these defective sites. Stated another way, a reduction in leak current is effective to a reduction in average current consumption.
As described above, in DRAM described in Japanese Patent Application Laid-open No. 8-203268, since bit lines are placed in a floating state during a non-access period, it is possible to cut off leak currents flowing through the bit lines and sense amplifiers connected thereto.
However, a problem still remains in that average current consumption cannot be sufficiently reduced for overall DRAM because the bit lines placed in the floating state alone fail to reduce leak currents flowing through word lines and current consumption in the peripheral circuits and the like.